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    • 专利摘要:
    Provided is a semiconductor device 1 according to the present invention which includes: a substrate 10 having a semiconductor chip arrangement surface 12; a semiconductor chip 20 disposed 5 on the semiconductor chip arrangement surface 12 and having a main electrode 24 and a control electrode 26 formed on a surface of the semiconductor chip 20 on a side opposite to a surface of the semiconductor chip 20 which opposedly faces the semiconductor chip arrangement surface 12, the control electrode 26 being formed at a position spaced apart from the main electrode 24; and a lead 30 having an electrode connecting member 32 at least a portion of which is joined to the main 10 electrode 24 via a solder 40, wherein, as viewed in a plan view, the electrode connecting member 32 has a projecting portion 38 projecting toward a semiconductor chip 20 side between an edge portion 37 of a joining surface 37 of the electrode connecting member 32 with the solder 40 on a gate electrode 26 side and the gate electrode 26 or at a position where the projecting portion 38 is in contact with the edge portion 37 of the joining surface 36 of the electrode connecting member 32 15 with the solder 40 on the gate electrode 26 side. According to the semiconductor device 1 of the present invention, it is possible to provide a semiconductor device whose reliability is minimally lowered.
    公开号:NL2022620A
    申请号:NL2022620
    申请日:2019-02-21
    公开日:2019-09-06
    发明作者:Nakagawa Masao；Kuwano Ryoji；Shinotake Yohei
    申请人:Shindengen Electric Mfg；
    IPC主号:
    专利说明:

    DESCRIPTION
    Title of the Invention: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    Technical Field [0001]
    The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
    Background Art [0002]
    Conventionally, there has been known a semiconductor device where a semiconductor chip and a lead are joined to each other via a solder (for example, see patent literature 1).
    [0003]
    As shown in Fig. 8, a conventional semiconductor device 900 described in patent literature 1 includes: a substrate 910 having a semiconductor chip arrangement surface 912; a semiconductor chip 920 disposed on the semiconductor chip arrangement surface 912, the semiconductor chip 920 having a collector electrode 922 formed on a surface of the semiconductor chip 920 which opposedly faces the semiconductor chip arrangement surface 912, and an emitter electrode 924 (main electrode) and a gate electrode 926 (control electrode) both formed on a surface of the semiconductor chip 920 on a side opposite to the surface which opposedly faces the semiconductor chip arrangement surface 912, the gate electrode 926 formed at a position spaced apart from the emitter electrode 924; and a lead 930 having an electrode connecting member 932 which is joined to the emitter elec trode 924 via a solder 940.
    [0004]
    In the conventional semiconductor device 900 described in patent literature 1, the electrode connecting member 932 is joined to the emitter elec trode 924 via the solder 940. That is, the semiconductor chip 920 and the lead 930 are directly joined to each other only via the solder 940 (without via an interposing member such as a wire). Accordingly, the semiconductor device 900 has a large current capacitance and hence, the semiconductor device 900 is a semiconductor device suitably used in electronic equipment (for example, a power source) which uses a large current. In the conventional semiconductor device 900 disclosed in patent literature 1, a solder material in a paste form is used for forming a solder.
    Citation Fist
    Patent Literature [0005]
    PTL 1: JP 2010-123686 A
    PTL2: JP 2017-199809 A
    Summary of Invention
    Technical Problem [0006]
    However, in the conventional semiconductor device disclosed in patent literature 1, there is a concern that, at the time of reflow soldering in a manufacturing step of the semiconductor device, a solder material or a flux is scattered due to rapid vaporization of a flux in the solder material in a paste form so that a solder (a solder ball SB) or a flux adheres to a surface of the gate electrode 926 (see Fig. 9). In this case, a joining strength between the gate electrode 926 and a wire 970 is lowered in a succeeding wire bonding step thus giving rise to a drawback that reliability of the semiconductor device may be lowered.
    Particularly, in a case where it is necessary to maintain a thickness of a solder to a fixed thickness or more to relax a stress (for example, a thermal stress) which acts on a solder between a semiconductor chip and a lead (for example, see patent literature 2), a solder or a flux which is scattered from an upper portion of a side surface of the solder material (the portion positioned high when the semiconductor chip is used as a reference) reaches far beyond a certain fixed distance and hence, the above-mentioned drawback becomes more conspicuous.
    [0007]
    The present invention has been made to overcome the above-mentioned drawbacks, and it is an object of the present invention to provide a semiconductor device w'hose reliability is minimally lowered. It is another object of the present invention to provide a method of manufacturing a semiconductor device for manufacturing such a semiconductor device.
    [0008] [1] A semiconductor device according to the present invention includes: a substrate having a semiconductor chip arrangement surface; a semiconductor chip disposed on the semiconductor chip arrangement surface and having a main electrode and a control electrode formed on a surface of the semiconductor chip on a side opposite to a surface of the semiconductor chip which opposedly faces the semiconductor chip arrangement surface, the control electrode being formed at a position spaced apart from the main electrode; and a lead having an electrode connecting member at least a portion of which is joined to the main electrode via a solder, wherein as viewed in a plan view, the electrode connecting member has a projecting portion projecting toward a semiconductor chip side between an edge portion of a joining surface of the electrode connecting member with the solder on a control electrode side and the control electrode or at a position where the projecting portion is in contact with the edge portion of the joining surface of the electrode connecting member with the solder on the control electrode side.
    [0009] [2] In the semiconductor device according to the present invention, it is preferable that the projecting portion be, as viewed in a plan view, disposed within a region where the semiconductor chip is disposed.
    [0010] [3] In the semiconductor device according to the present invention, it is preferable that the projecting portion be not in contact with the semiconductor chip.
    [0011] [4] In the semiconductor device according to the present invention, it is preferable that the projecting portion be formed on the electrode connecting member with an arrangement configuration capable of blocking reaching of a solder ball scattered from a side surface of the solder to the control electrode in a joining step of joining the main electrode and the electrode connecting member to each other by the solder.
    [0012] [5] In the semiconductor device according to the present invention, it is preferable that, as viewed in cross section, the lead be bent toward a semiconductor chip side at a portion of the projecting portion. [0013] [6] In the semiconductor device according to the present invention, it is preferable that, as viewed from a surface of the electrode connecting member on a side opposite to the surface of the electrode connecting member which opposedly faces the semiconductor chip arrangement surface, a recessed portion which corresponds to the projecting portion be formed on the electrode connecting member. [0014] [7] In the semiconductor device according to the present invention, it is preferable that, as viewed in a plan view, the electrode connecting member be disposed so as to cover the whole solder.
    [0015] [8] A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device for manufacturing the semiconductor device described in any one of the above-mentioned [1] to [7], The method of manufacturing a semiconductor device includes: a semiconductor chip arrangement step of arranging a semiconductor chip on a semiconductor chip arrangement surface of a substrate having the semiconductor chip arrangement surface such that a main electrode and a control electrode formed at a position spaced apart from the main electrode are positioned on a surface of the semiconductor chip on a side opposite to a surface of the semiconductor chip which opposedly faces the semiconductor chip arrangement surface; an assembled body forming step of forming an assembled body by arranging a lead having an electrode connecting member which forms a projecting portion on one surface thereof in a projecting manner in a state where the main electrode and the electrode connecting member opposedly face each other with a solder material sandwiched therebetween, in a state where, as viewed in a plan view, the projecting portion is positioned between an edge portion of a joining surface of the electrode connecting member with the solder material on a control electrode side and the control electrode or at a position where the projecting portion is in contact with the edge portion of the joining surface of the electrode connecting member with the solder material on the control electrode side, and in a state where the projecting portion projects toward a semiconductor chip side; and a joining step of joining the main electrode and the electrode connecting member to each other via a solder by solidifying the solder material after melting the solder material. [Advantageous effects of the invention] [0016]
    According to the semiconductor device of the present invention, as viewed in a plan view, the electrode connecting member has the projecting portion projecting toward the semiconductor chip side between the edge portion of the joining surface of the electrode connecting member with the solder on the gate electrode side and the gate electrode or at the position where the projecting portion is in contact with the edge portion of the joining surface of the electrode connecting member with the solder on the gate electrode side. Accordingly, even when a solder or a flux is scattered due to rapid vaporization of the flux in a solder material at the time of reflowing the solder material in the joining step during a manufacturing process, a scattered solder or a scattered flux impinges on the projecting portion and hence, the solder or the flux minimally adheres to the surface of the control electrode by the projecting portion. Accordingly, a joining strength between the control electrode and the wire is minimally lowered in the succeeding wire bonding step so that reliability of the semiconductor device is minimally lowered.
    [0017]
    In the semiconductor device of the present invention, as viewed in a plan view, the electrode connecting member has the projecting portion projecting toward the semiconductor chip side between the edge portion of the joining surface of the electrode connecting member with a solder on a control electrode side and the control electrode or at a position where the projecting portion is in contact with the edge portion of the joining surface of the electrode connecting member with the solder on the control electrode side. Accordingly, even in a case where a solder or a flux scattered from an upper portion of a side surface of a solder material due to the necessity of maintaining a thickness of the solder to a certain fixed thickness or more is likely to scatter to reach a place far beyond a certain fixed distance, most of the solder or the flux scattered from the upper portion of the side surface of the solder material impinges on the projecting portion. Accordingly, a solder or a flux minimally adheres to the surface of the control elec trode and hence, a joining strength between the control electrode and the wire is further minimally lowered in the succeeding wire bonding step so that the reliability of the semiconductor device is further minimally lowered. [0018]
    The method of manufacturing a semiconductor device of the present invention includes: the assembled body forming step of forming an assembled body while arranging the lead having the electrode connecting member which forms the projecting portion on one surface thereof in a projecting manner in a state where the main electrode and the electrode connecting member opposedly face each other with a solder material sandwiched therebetween, in a state where, as viewed in a plan view, the projecting portion is positioned between the edge portion of the joining surface of the electrode connecting member with the solder material on the control electrode side and the control electrode or at a position where the projecting portion is in contact with the edge portion of the joining surface of the electrode connecting member with the solder material on the control electrode side, and in a state where the projecting portion projects toward the semiconductor chip side; and the joining step of joining the main electrode and the electrode connecting member to each other via a solder by solidifying the solder material after melting the solder material. Accordingly, even when a solder or a flux is scattered due to rapid vaporization of a flux in the solder material in the joining step, the scattered solder or the flux impinges on the projecting portion and hence, the solder or the flux minimally adheres to the surface of the control electrode by the projecting portion. Accordingly, a joining strength between the control electrode and the wire is minimally lowered in the succeeding wire bonding step thus manufacturing a semiconductor device where reliability is minimally lowered.
    Brief Description of Drawings [0019]
    Fig. 1 is a view showing a semiconductor device 1 according to an embodiment 1. Fig. 1(a) is a plan view of the semiconductor device 1, and Fig. 1(b) is a cross-sectional view of the semiconductor device 1.
    Fig. 2 is an enlarged view of an essential part of the semiconductor device 1 according to the embodiment 1. Fig. 2(a) is an enlarged cross-sectional view of the essential part of the semiconductor device 1, and Fig. 2(b) is an enlarged plan view of the essential part of the semiconductor device 1.
    Fig. 3 is a view showing steps of a method of manufacturing a semiconductor device according to the embodiment 1. Fig. 3(a) is a view showing a substrate preparation step S100, Fig. 3(b) is a view showing a semiconductor chip arrangement step S200, and Fig. 3(c) is a view showing a solder material arrangement step S310.
    Fig. 4 is a view showing steps of the method of manufacturing a semiconductor device according to the embodiment 1. Fig. 4(a) is a view showing a lead frame arrangement step S320,
    Fig. 4(b) is a view' showing a wire bonding step S500, and Fig. 4(c) is a view' showing a resin sealing step S600.
    Fig. 5 is a view showing a semiconductor device 2 according to an embodiment 2. Fig.
    5(a) is an enlarged cross-sectional view of the semiconductor device 2, and Fig. 5(b) is an enlarged plan view' of an essential part of the semiconductor device 2.
    Fig. 6 is an enlarged cross-sectional view of an essential part of a semiconductor device 3 according to a modification 1.
    Fig. 7 is a view' showing a semiconductor device 4 according to a modification 2. Fig. 7(a) is a perspective view of the semiconductor device 2, Fig. 7(b) is a cross-sectional view taken along a line B-B in Fig. 7(a), and Fig. 7(c) is a cross-sectional view' taken along a line C-C in Fig. 7(a).
    Fig. 8 is a cross-sectional view of a conventional semiconductor device 900. hi Fig. 8, symbol 946 indicates a solder, symbols 960, 962 indicate terminals, symbol 970 indicates a wire, and symbol 980 indicates a resin.
    Fig. 9 is an enlarged cross-sectional view of an essential part of the conventional semiconductor device 900 showing a drawback which the conventional semiconductor device 900 has. Symbol 941 indicates a solder material (solder material in a paste form).
    Description of Embodiments [0020]
    Hereinafter, a method of manufacturing a semiconductor device according to the present invention is described based on embodiments shown in the drawings. The respective drawings are schematic view's, and do not always strictly reflect actual sizes.
    [0021] [Embodiment 1]
    1. Configuration of semiconductor device 1 according to embodiment 1
    The semiconductor device 1 according to the embodiment 1 is a semiconductor device w'here, to relax a stress (a thermal stress, for example) which acts on a solder between a semiconductor chip and a lead, a thickness of the solder is set to a fixed thickness or more.
    As shown in Fig. 1 and Fig. 2, the semiconductor device 1 according to the embodiment includes a substrate 10, a semiconductor chip 20, leads 30, 62, 64, solders 40, 46, and a wire 70. These components are resin-sealed by a resin 80 except for external connecting terminals of the leads 30, 62, 64 and a portion of a heat-radiation metal plate 18.
    [0022]
    The substrate 10 is a substrate having a semiconductor chip arrangement surface 12. A suitable substrate (for example, a printed-circuit board) can be used as the substrate 10. However, in the embodiment 1, a direct copper bonding (DCB) substrate which has an insulating substrate 14, a circuit 16 formed on one surface of the insulating substrate 14 and having a semiconductor chip arrangement surface 12, and a heat-radiation metal plate 18 formed on the other surface of the insulating substrate 14 is used. A portion of the heat-radiation metal plate 18 is exposed from the resin 80.
    [0023]
    The semiconductor chip 20 is an insulated gate bipolar transistor (1GBT) disposed on the semiconductor chip arrangement surface 12. The semiconductor chip 20 has: a collector electrode 22 formed on one surface (a surface which opposedly faces the semiconductor chip arrangement surface 12); and an emitter electrode 24 (main electrode) and a gate electrode 26 (control electrode) formed on the other surface (a surface on a side opposite to the surface which opposedly faces the semiconductor chip arrangement surface 12). The gate electrode 26 is formed at a position spaced apart from the emitter electrode 24.
    [0024]
    The collector electrode 22 is joined to the semiconductor chip arrangement surface 12 of the substrate 10 via a solder 46, and the collector electrode 22 is connected to the outside via the solder 46, the substrate 10 (circuit 16), and the lead 64.
    The emitter electrode 24 is joined to an electrode connecting member 32 of the lead 30 via a solder 40, and the emitter electrode 24 is connected to the outside via the solder 40 and the lead 30 (an external connecting terminal 34).
    [0025]
    The leads 30, 62, 64 are flat-plate-like metal members and are formed by cutting out portions of a lead frame. The leads 30, 62, 64 respectively have a larger cross-sectional area than a wire so that a large electric current can flow through the leads 30, 62, 64.
    [0026]
    The lead 30 has the electrode connecting member 32, and a portion of the electrode connecting member 32 is joined to the emitter electrode 24 via the solder 40. To be more specific, the electrode connecting member 32 which has the portion thereof joined to the emitter electrode 24 via the solder 40 is provided to one end portion of the lead 30, while the external connecting terminal 34 for connecting the lead 30 to the outside is provided to the other end portion of the lead 30. The lead may have the electrode connecting member 32 which is formed of an electrode connecting member wholly joined to the emitter electrode 24 via the solder 40. For example, the lead may have an electrode connecting member having an L shape, and the whole surface of the electrode connecting member on a solder material side may be brought into contact with an upper surface and a side surface of the solder material.
    [0027]
    The electrode connecting member 32 is disposed so as to cover the whole solder 40 as viewed in a plan view. The electrode connecting member 32 has a projecting portion 38 projecting toward the semiconductor chip 20 side between an edge portion 37 of a joining surface 36 of the electrode connecting member 32 to the solder 40 on a gate electrode 26 side and the gate electrode 26.
    [0028]
    The projecting portion 38 is provided to the electrode connecting member 32 with an arrangement configuration which can block (prevent) reaching of a solder ball (see Fig. 9) scattered from a side surface of the solder 40 (a side surface of a solder material 41 described later) in the joining step of joining the emitter electrode 24 and the electrode connecting member 32 to each other by the solder 40 to the gate electrode 26.
    That is, a solder ball performs a parabolic motion (an oblique projection or a horizontal projection) after the solder ball is scattered from the side surface of the solder material. Accordingly, the projecting portion 38 is formed such that the projecting portion is disposed on a parabolic curve which passes a point on the surface of the gate electrode and a point on the side surface of the solder material 41 (a trajectory of the parabolic motion) within an initial speed in general at which the solder ball or the flux is jetted from the solder material 41 when a solder or a flux is scattered. In other words, the projecting portion 38 is provided to the electrode connecting member 32 at the position and with the configuration where a parabolic curve passing a point on the surface of the gate electrode 26 and a point on the side surface of the solder material 41 passes within an initial speed in general at w'hich a solder ball or a flux is jetted from the solder material 41 w'hen a solder or the flux is scattered.
    [0029]
    The projecting portion 38 is disposed at the position where the gate electrode 26 is concealed by the projecting portion 38 as viewed from a portion of the side surface of the solder 40 (solder material 41) (for example, the position of the side surface of the solder material remotest from the semiconductor chip) in the joining step.
    With respect to a width of the projecting portion 38 (a width of the projecting portion 38 in a direction orthogonal to a direction from the solder material 41 toward the gate electrode 26), the width may be set such that the width allows the projecting portion 38 to conceal the gate electrode 26 as viewed from a portion of the solder material 41 (for example, a position of the side surface of the solder material remotest from the semiconductor chip).
    The arrangement position and the height of the projecting portion 38 may be set such that the arrangement position and the height of the projecting portion 38 allows a portion of the projecting portion 38 to be disposed on a parabolic curve passing a point on the surface of the gate electrode and a point on the side surface of the solder material 41 between the solder material 41 and the gate electrode 26. Accordingly, w'hen a distance between the gate electrode 26 and the emitter electrode 24 is short, it is necessary to decrease a distance between the side surface of the solder material 41 and the projecting portion 38 or to increase a height of the projecting portion. On the other hand, when the distance between the gate electrode 26 and the emitter electrode 24 is long, the height of the projecting portion 38 may be set lower than a predetermined height.
    [0030]
    The projecting portion 38 is disposed within a region where the semiconductor chip 20 is disposed as viewed in a plan view. That is, the projecting portion 38 is disposed directly above the semiconductor chip 20. The lead 30 is bent toward the semiconductor chip 20 side at a portion of the projecting portion 38 as viewed in a cross section. Accordingly, as viewed from a surface of the electrode connecting member 32 on a side opposite to a surface of the electrode connecting member 32 which opposedly faces the semiconductor chip arrangement surface 12, a recessed portion corresponding to the projecting portion 38 is formed on the electrode connecting member 32, and a resin also enters the recessed portion. The projecting portion 38 is not in contact with the semiconductor chip 20.
    [0031]
    In the embodiment 1, assuming a height of the projecting portion 38 as “h” and a distance between the surface of the emitter electrode (main electrode) of the semiconductor chip 20 and the surface of the electrode connecting member 32 as “d” using the surface of the electrode connecting member 32 which opposedly faces the semiconductor chip arrangement surface 12 as a reference, a relationship of 0.8d<h<0.95d is satisfied. Accordingly, the projecting portion 38 is not in contact with the semiconductor chip 20.
    [0032]
    One end portion of the lead 62 is connected to the gate electrode 26 via a wire 70, and the other end portion of the lead 62 forms a terminal for connection with the outside. One end portion of the lead 64 is connected to the circuit 16 which is connected with the collector electrode 22, and the other end portion of the lead 64 forms a terminal for connection with the outside.
    [0033]
    The solders 40, 46 are made of an alloy or metal having conductivity and adhesiveness. The solders 40, 46 are formed by melting the solder materials 41,45 by heating and by solidifying the melted solder materials 41, 45.
    The solder 40 joins the emitter electrode 24 and the electrode connecting member 32 to each other. A thickness (solder thickness) of the solder 40 is larger than a thickness of the solder 46 (the solder between the substrate 10 and the semiconductor chip 20). The thickness of the solder 40 is 300 pm or more, for example. The solder 40 is made of a solder material in a paste form containing a flux (a so-called cream solder).
    The solder 46 joins the collector electrode 22 and the semiconductor chip arrangement surface 12 to each other.
    The solder 46 is made of a solder material in a paste form (for example, a so-called cream solder) containing a solvent (for example, a flux), is disposed on the semiconductor chip arrangement surface 12 of the substrate 10 by printing, and joins the substrate 10 and the semiconductor chip 20 to each other by heating using a reflow method. With respect to the solder 46 between the substrate 10 and the semiconductor chip 20, unlike the solder 40 between the semiconductor chip 20 and the lead 30, there is no circumference that a stress (for example, a thermal stress) acting on the solder 46 is relaxed. Further, when a thickness of the solder 46 is increased, a conduction loss is increased. Accordingly, unlike the solder 40 between the semiconductor chip 20 and the lead 30, it is preferable that the solder 46 between the substrate 10 and the semiconductor chip 20 have a relatively small thickness.
    [0034]
    A suitable resin can be used as the resin 80.
    [0035]
    2. Method of manufacturing semiconductor device according to embodiment 1
    The method of manufacturing a semiconductor device according to the embodiment 1 includes: a substrate preparation step S100, a semiconductor chip arrangement step S200, an assembled body forming step S300, a joining step S400, a wire bonding step S500, a resin sealing step S600, and a lead working step S700.
    [0036] (1) Substrate preparation step SI00
    In the substrate preparation step SI00, the substrate 10 is prepared (see Fig.3 (a)). To be more specific, the substrate 10 is positioned and disposed on a predetermined jig (not shown in the drawing).
    [0037] (2) Semiconductor chip arrangement step S200
    In the semiconductor chip arrangement step S200, the semiconductor chip 20 is disposed on the semiconductor chip arrangement surface 12 of the substrate 10 having the semiconductor chip arrangement surface 12 via the solder material 45. That is, the semiconductor chip 20 is disposed such that the emitter electrode 24 (main electrode) and the gate electrode 26 (control electrode) are positioned on the surface of the semiconductor chip 20 on a side opposite to the surface of the semiconductor chip 20 which opposedly faces the semiconductor chip arrangement surface 12 (see Fig. 3(b)). The gate electrode 26 is formed at a position spaced apart from the emitter electrode 24. To be more specific, firstly, the solder material 45 in a paste form (for example, a so-called cream solder) is disposed (to be more specific, printed) on the semiconductor chip arrangement surface 12 of the substrate 10. Next, the semiconductor chip 20 is disposed on the semiconductor chip arrangement surface 12 in a state where the semiconductor chip arrangement surface 12 and the collector electrode 22 of the semiconductor chip 20 opposedly face each other via the solder material 45. Accordingly, on the surface of the semiconductor chip 20 on a side opposite to the surface of the semiconductor chip 20 which opposedly faces the semiconductor chip arrangement surface 12, the emitter electrode 24 and the gate electrode 26 formed at a position spaced apart from the emitter electrode 24 are disposed.
    [0038] hi the embodiment 1, the solder material 45 is printed on the semiconductor chip arrangement surface 12. However, the solder material may be supplied in a suitable method such as supplying the solder material by a dispenser, supplying the solder material in the form of a wire solder fed by a solder feeder or the like or supplying the solder material by making a melted solder material flow onto the semiconductor chip arrangement surface 12. Cream solder is a solder formed into a paste form with appropriate viscosity by adding a flux to powdery solder. A flux is a component which is vaporized at a high temperature (for example, a melting temperature of a solder). As a flux, a resin-based flux which uses a rosin, a modified rosin, a synthetic resin or the like as a main component is used. A thixotropic agent, an activator, a solvent for an activator, a dispersion stabilizing agent or the like may be added to a flux.
    [0039] (3) Assembled body forming step S300
    The assembled body forming step S300 includes a solder material arrangement step S310 and a lead frame arrangement step S320.
    [0040] (3-1) Solder material arrangement step S310
    In the solder material arrangement step S310, the solder material 41 is disposed on the emitter electrode 24 of the semiconductor chip 20 (see Fig. 3(c)). As the solder material 44, a solder material in a paste form (a so-called cream solder) containing a flux is used. Various methods are considered as a method of supplying a solder material in a paste form. However, fine adjustment of an amount of solder and accuracy in a place to which solder is supplied are necessary for supplying a solder material in a paste form onto the emitter electrode 24 and hence, it is preferable to supply a solder material in a paste form using a dispenser.
    [0041] (3-2) Lead frame arrangement step S320
    In the lead frame arrangement step, the lead 30 (a lead frame to which the lead 30 is connected) having the electrode connecting member 32 which is joined to the main electrode via the solder is disposed on the semiconductor chip 20 in a state where the projecting portion 38 of the electrode connecting member 32 projects toward the semiconductor chip 20 side between the edge portion 37 of the joining surface of the electrode connecting member 32 with the solder 40 on a gate electrode 26 side and the gate electrode 26 as viewed in a plan view (and the projecting portion 38 is not in contact with the semiconductor chip 20) (see Fig. 4(a)). At this stage of the operation, the leads 62, 64 (the lead 64 shown in Fig. 1) of the lead frame are disposed at predetermined positions. [0042]
    With such operations, it is possible to form the assembled body where the lead 30 having the elec trode connecting member 32 which forms the projecting portion 38 on one surface thereof in a projecting manner is arranged in a state where the emitter electrode 24 and the electrode connecting member 32 opposedly face each other with the solder material 41 sandwiched therebetween, in a state where, as viewed in a plan view, the projecting portion 38 is positioned between the edge portion of the joining surface of the electrode connecting member 32 with the solder material 41 on the gate electrode 26 side and the gate electrode 26, and in a state where the projecting portion 38 projects toward the semiconductor chip 20 side as viewed in cross section.
    [0043] (4) Joining step (reflow step) S400
    In the joining step (reflow step) S400, the assembled body 50 is conveyed into and is heated by a reflow furnace (not shown in the drawings) so as to melt the solder materials 41, 45. After melting the solder materials 41, 45, the solder materials 41,45 are solidified and formed into the solders 40, 46. Accordingly, the semiconductor chip arrangement surface 12 of the substrate 10 and the emitter elec trode 24 of the semiconductor chip 20 are joined to each other via the solder 46, and the collector electrode 22 of the semiconductor chip 20 and the electrode connecting member 32 of the lead 30 are joined to each other via the solder 40.
    [0044]
    In the joining step S400, there may be a case where a solder material and a flux scatter due to rapid vaporization of a flux in the solder material 41. However, the electrode connecting member 32 has, as viewed in a plan view, the projecting portion 38 projecting toward a semiconductor chip 20 side between the edge portion 37 of the joining surface of the electrode connecting member 32 with the solder 40 on a gate electrode 26 side and the gate electrode 26. Accordingly, a solder ball or a scattered flux impinges on the projecting portion 38 so that it is possible to prevent a solder or a flux from adhering to the surface of the gate electrode 26. Further, on an upper surface of the solder material 41, it is possible to prevent a scattered solder or a scattered flux from adhering to the gate electrode 26 by the electrode connecting member 32.
    [0045] (5) Wire bonding step S500
    Next, the gate electrode 26 and the lead 62 (see Fig. 1) are connected to each other by the wire 70 (see Fig. 4(b)). A suitable wire is used as the wire 70.
    [0046] (6) Resin sealing step S600 and lead working step S700
    Next, the assembled body 50 is resin-sealed by the resin 80 except for the external terminals of the leads 30, 62,64 and the metal plate 18 for heat radiation (resin sealing step S600, see Fig. 4(c)). Next, the leads 30, 62, 64 are separated from the lead frame by cutting, and working such as bending is applied to predetermined portions (lead working step S700, not shown in the drawings).
    The semiconductor device 1 according to the embodiment 1 can be manufactured in accordance with the above-mentioned steps.
    [0047]
    3. Advantageous effects acquired by semiconductor device 1 and method of manufacturing semiconductor device according to embodiment 1
    According to the semiconductor device 1 of the embodiment 1, as viewed in a plan view, the electrode connecting member 32 has the projecting portion 38 projecting toward the semiconductor chip 20 side between the edge portion 37 of the joining surface of the electrode connecting member 32 with the solder 40 on the gate electrode 26 side and the gate electrode 26. Accordingly, even when a solder or a flux is scattered due to rapid vaporization of the flux in a solder material 41 at the time of reflowing the solder material in the joining step during a manufacturing process, a scattered solder or a scattered flux impinges on the projecting portion and hence, the solder or the flux minimally adheres to the surface of the gate electrode 26 by the projecting portion 38. Accordingly, a joining strength between the gate electrode 26 and the wire 70 is minimally lowered in the succeeding wire bonding step so that reliability of the semiconductor device 1 is minimally lowered.
    [0048]
    Further, in the semiconductor device 1 according to the embodiment 1, the electrode connecting member 32 has the projecting portion 38 projecting toward the semiconductor chip 20 side. Accordingly, even in a case where a solder or a flux scattered from the upper portion of the side surface of the solder material 41 (from a position remotest from the semiconductor chip) is likely to scatter to reach a place far beyond a certain fixed distance attributed to maintaining of a thickness of the solder 40 to a certain fixed thickness or more, most of a solder and a flux scattered from the upper portion of the side surface of the solder material 41 impinge on the projecting portion 38. Accordingly, a solder and a flux minimally adhere to the surface of the gate electrode 26. Accordingly, a joining strength between the gate electrode 26 and the wire 70 is further minimally lowered in the succeeding wire bonding step and hence, the reliability of the semiconductor device 1 is further minimally lowered.
    [0049]
    In the semiconductor device 1 according to the embodiment 1, the projecting portion 38 is disposed within the region where the semiconductor chip 20 is disposed as viewed in a plan view. Accordingly, the projecting portion 38 can be disposed between the emitter electrode 24 and the gate electrode 26 on the semiconductor chip 20 with certainty.
    [0050]
    In the semiconductor device I according to the embodiment 1, the projecting portion 38 is not in contact with the semiconductor chip 20 and hence, there is no possibility that a drawback such as the occurrence of deviation in a current flow occurs.
    The semiconductor device 1 according to the embodiment 1 is a semiconductor device where a thickness of the solder is maintained at a certain fixed thickness or more for relaxing a stress (for example, a thermal stress) which acts on the solder between the semiconductor chip and the lead. Accordingly, even when the projecting portion projecting toward the semiconductor chip 20 side is formed on the electrode connecting member 32 disposed on the semiconductor chip 20 side, the projecting portion 38 is not in contact with the semiconductor chip 20.
    [0051]
    In the semiconductor device 1 according to the embodiment 1, the projecting portion 38 is provided to the electrode connecting member 32 with an arrangement configuration capable of blocking reaching of a solder ball scattered from the side surface of the solder (solder material) to the gate electrode 26 in the joining step of joining the emitter electrode 24 and the electrode connecting member 32 to each other by the solder 40. Accordingly, even when a solder or a flux is scattered due to rapid vaporization of a flux in the solder material 41 at the time of reflowing the solder material 41 during a manufacturing process, it is possible to more easily prevent adhesion of a solder or a flux to the surface of the gate electrode 26 by the projecting portion 38. Accordingly, a joining strength between the gate electrode 26 and the wire 70 is further minimally lowered in a succeeding wire bonding step and hence, the reliability of the semiconductor device 1 is further minimally lowered.
    [0052]
    In the semiconductor device 1 according to the embodiment 1, assuming a height of the projecting portion 38 as “h”, and a distance between the surface of the emitter electrode of the semiconductor chip 20 and the surface of the electrode connecting member 32 which opposedly faces the semiconductor chip arrangement surface 12 as “d” using the surface of the electrode connecting member 32 which opposedly faces the semiconductor chip arrangement surface 12 as a reference, the relationship of 0.8d<h<0.95d is satisfied. Accordingly, most of the side surface of the solder material 41 can be covered by the projecting portion. As a result, even when a solder or a flux is scattered due to rapid vaporization of a flux in the solder material 41 at the time of reflowing the solder material 41 during a manufacturing process, most of the solder and the flux scattered from the side surface of the solder material 41 on a gate electrode 26 side impinge on the projecting portion 38. Accordingly, a solder or a flux minimally adheres to the surface of the gate electrode 26 and hence, a joining strength between the gate electrode 26 and the wire 70 is further minimally lowered in a succeeding wire bonding step so that the reliability of the semiconductor device 1 is further minimally lowered.
    Although there is a slight gap between a peak point of the projecting portion 38 and the semiconductor chip 20, even when a solder is scattered from a lower portion of the side surface of the solder material 41, there is no possibility that the solder reaches the gate electrode 26 and hence, such a gap does not cause a serious problem.
    [0053]
    In the semiconductor device 1 according to the embodiment 1, the lead 30 is bent toward the semiconductor chip 20 side at a portion of the projecting portion 38 as viewed in cross section and hence, the projecting portion 38 can be easily formed. Further, the projecting portion 38 is formed by bending the lead 30 and hence, the lead 30 and the resin 80 are minimally peeled off from each other thus increasing a joining strength between the resin 80 and the lead 30.
    [0054]
    In the semiconductor device 1 according to the embodiment 1, the recessed portion corresponding to the projecting portion 38 is formed on the electrode connecting member 32 as viewed from the surface of the electrode connecting member 32 on a side opposite to the surface of the electrode connecting member 32 on a semiconductor chip 20 side. Accordingly, the resin 80 filled in the resin sealing step S600 is also filled in the recessed portion so that the resin-sealing can be performed with the further higher adhesiveness between the resin 80 and the lead 30. Accordingly, a joining strength between the resin 80 and the lead 30 can be further increased. [0055]
    In the semiconductor device 1 according to the embodiment 1, the electrode connecting member 32 is disposed so as to cover the whole solder 40 as viewed in a plan view. Accordingly, it is possible to prevent scattering of a solder or a flux from an upper side of the solder material 41 by the electrode connecting member 32. That is, in the semiconductor device 1 according to the embodiment 1, it is possible to prevent scattering of a solder or a flux to a remote place in such a manner that scattering of the solder or the flux from the upper side of the solder material 41 is prevented by the electrode connecting member 32, and scattering of the solder or the flux from the side surface of the solder material 41 is prevented by the projecting portion 38. Accordingly, it is possible to further easily prevent a solder or a flux from adhering to the surface of the gate electrode 26 and hence, a joining strength between the gate electrode 26 and the wire 70 is further minimally lowered in a succeeding wire bonding step thus making the reliability of the semiconductor device 1 minimally lowered.
    [0056]
    In the semiconductor device 1 according to the embodiment 1, a thickness of the solder is 300 ttm or more. Accordingly, a stress (for example, a thermal stress) which acts on the solder 40 between the semiconductor chip 20 and the lead 30 can be relaxed and hence, a drawback such as the occurrence of a crack in the solder 40 minimally occurs. As a result, it is possible to manufacture a highly reliable semiconductor device. From this point of view, to make the above-mentioned drawback minimally occur, it is preferable that a thickness of the solder 40 be 400 pm or more, and it is more preferable that the thickness of the solder 40 be 500 pm or more.
    [0057]
    The method of manufacturing a semiconductor device according to the embodiment 1 includes the assembled body forming step of forming the assembled body 50 by arranging the lead 30 having the electrode connecting member 32 which forms the projecting portion 38 on one surface thereof in a projecting manner in a state where the emitter electrode 24 and the electrode connecting member 32 opposedly face each other with the solder material 41 sandwiched therebetween, in a state where, as viewed in a plan view, the projecting portion 38 is positioned between the edge portion 37 of the joining surface of the electrode connecting member 32 with the solder material 41 on a gate electrode side and the gate electrode or at a position where the projecting portion 38 is in contact with the edge portion 37 of the joining surface 36 of the electrode connecting member 32 with the solder material 41 on a gate electrode side, and in a state where the projecting portion 38 projects toward the semiconductor chip 20 side. Accordingly, even when a solder or a flux is scattered due to rapid vaporization of a flux in the solder material 41 in the joining step, it is possible to prevent a solder or a flux from adhering to the surface of the gate electrode by the projecting portion 38. Accordingly, a joining strength between the gate electrode 26 and the wire 70 is minimally lowered in a succeeding wire bonding step thus it is possible to manufacture a semiconductor device whose reliability is minimally lowered.
    [0058] [Embodiment 2]
    A semiconductor device 2 according to an embodiment 2 basically has substantially the same configuration as the semiconductor device according to the embodiment 1. However, the semiconductor device 2 according to the embodiment 2 differs from the semiconductor device 1 according to the embodiment 1 with respect to a position of a projecting portion. That is, in the semiconductor device 2 according to the embodiment 2, as viewed in a plan view, a projecting portion 38a projecting toward a semiconductor chip 20 side is disposed not between an edge portion 37 of a joining surface of an electrode connecting member with a solder 40 on a gate electrode 26 side and a gate electrode 26, but at a position where the projecting portion 38a is in contact with the edge portion 37 of the joining surface of the electrode connecting member 32 with the solder 40 on the gate electrode 26 side (see Fig. 5).
    [0059]
    With respect to the projecting portion 38a, a portion of the projecting portion 38a on a solder 40 side (a side surface and a peak portion on a solder 40 side) is in contact with an upper side and an approximately center portion of a side surface of the solder 40. An outer shape of the solder 40 ranging from the peak portion of the projecting portion 38a to an emitter electrode 24 is formed in a fillet shape or a rounded shape.
    [0060]
    In this manner, the semiconductor device 2 according to the embodiment 2 differs from the semiconductor device 1 according to the embodiment 1 with respect to the position of the projecting portion. However, an electrode connecting member 32 has the projecting portion 38a projecting toward the semiconductor chip 20 side at a position where the projecting portion 38a is in contact with the edge portion 37 of the joining surface 36 of the electrode connecting member 32 with the solder 40 on the gate electrode 26 side as viewed in a plan view. Accordingly, even when a solder or a flux is scattered due to rapid vaporization of the flux in a solder material at the time of reflowing a solder material in a joining step during a manufacturing process, a scattered solder or a scattered flux impinges on the projecting portion and hence, the solder or the flux minimally adheres to a surface of the gate electrode 26 by the projecting portion 38a. As a result, a joining strength between the gate electrode 26 and a wire 70 is minimally lowered in a succeeding wire bonding step so that reliability of the semiconductor device 2 is minimally lowered.
    [0061]
    In the semiconductor device 2 according to the embodiment 2, the electrode connecting member 32 has the projecting portion 38a projecting toward the semiconductor chip 20 side at the position where the projecting portion 38a is in contact with the edge portion 37 of the joining surface 36 of the electrode connecting member 32 with the solder 40 on a gate electrode 26 side as viewed in a plan view. Accordingly, one side surface and the peak portion of the projecting portion 38a are brought into contact with the upper portion and the center portion of the side surface of the solder 40 respectively and hence, a joining area between the solder 40 and a lead 30 is increased. As a result, a joining strength between the solder 40 and the lead 30 is increased and hence, reliability of the semiconductor device 2 is enhanced.
    [0062]
    The semiconductor device 2 according to the embodiment 2 has substantially the same configuration as the semiconductor device 1 according to the embodiment 1 except for the position of the projecting portion and hence, the semiconductor device 2 according to the embodiment 2 acquires the corresponding advantageous effects found amongst all advantageous effects which the semiconductor device 1 according to the embodiment 1 acquires.
    [0063]
    Although the present invention has been described heretofore based on the above-mentioned respective embodiments, the present invention is not limited to the above-mentioned respective embodiments. Various modifications can be carried out in various modes without departing from the gist of the present invention, and the following modifications are also conceivable, for example.
    [0064] (1) The materials, the shapes, the positions, the sizes and the like described in the above-mentioned respective embodiments are provided for an exemplifying purpose, and can be modified within a range where the advantageous effects of the present invention are not jeopardized.
    [0065] (2) In the above-mentioned respective embodiments, the projecting portion may be formed by increasing a thickness of a portion of a lead 30 (a projecting portion 38b of a semiconductor device 3 according to a modification 1 shown in Fig. 6).
    [0066] (3) In the above-mentioned respective embodiments, the semiconductor device having one semiconductor chip is exemplified as the semiconductor de vice of the present invention. However, the present invention is not limited to such a semiconductor device. For example, a semiconductor device may have two semiconductor chips (see Fig. 7), or may have three or more semiconductor chips.
    [0067]
    As the semiconductor device having two semiconductor chips, for example, a following semiconductor device where two semiconductor chips are connected to each other in cascode connection is named (see a semiconductor device 4 of a modification 2 shown in Fig. 7). In the semiconductor device 4 of the modification 2, an emitter electrode 24a of a semiconductor chip 20c is electrically connected to a lead 30c. A collector electrode 22c of the semiconductor chip 20c is electrically connected to a lead 30d via a circuit 16c of a substrate 10c, and is also electrically connected to an emitter electrode 24d of a semiconductor chip 20d via the lead 30d. Although not shown in the drawings, a collector electrode 22d of the semiconductor chip 20d is connected to a lead 66 via a circuit 16d (see Fig. 7(a) and Fig. 7(b)). Also in the semiconductor device having such a configuration, a projecting portion may be formed on the leads 30c, 30d respectively (see Fig. 7(c) where projecting portion 38c is formed on the lead 30c).
    [0068] (4) In the above-mentioned respective embodiments, the projecting portion is formed only on the side of the joining surface 36 of the electrode connecting member 32 with the solder 40 on the gate electrode 26 side. However, the present invention is not limited to such a configuration. A projecting portion may be formed on a portion other than the side of the joining surface 36 of the electrode connecting member 32 with the solder 40 on the gate electrode 26 side. With such a configuration, it is possible to prevent a solder or a flux from being scattered to the portion other than the gate electrode and hence, it is possible to provide a semiconductor device whose reliability is further minimally lowered.
    [0069] (5) In the above-mentioned respective embodiments, an IGBT having three terminals is used as the semiconductor chip 20. However, the present invention is not limited to such a semiconductor chip. The semiconductor chip 20 may be any other semiconductor elements each having three terminals (for example, a MOSFET). The semiconductor chip 20 may be a semiconductor element having two terminals (for example, a diode). The semiconductor chip 20 may be a semiconductor element having four or more terminals (for example, a thyristor may be used as a semiconductor element having four terminals).
    [0070] (6) In the above-mentioned respective embodiments, a so-called vertical-type semiconductor device w'here a collector electrode is disposed on one surface of a semiconductor chip, and an emitter electrode and a gate electrode are disposed on the other surface of the semiconductor chip is used as the semiconductor device of the present invention. However, the present invention is not limited to such a semiconductor device. For example, a so-called lateral-type semiconductor device which has all electrodes on one surface of a semiconductor chip may be used as the semiconductor device of the present invention.
    Reference Signs List [0071]
    1, 2, 3, 4: semiconductor device
    10, 10a, 10b, 10c, lOd: substrate
    12, 12a, 12b, 12c, 12d: chip arrangement surface
    14, 14a, 14b, 14c, 14d: insulating substrate
    16, 16a, 16b, 16c, 16d: circuit
    18, 18a, 18b, 18c, 18d: metal plate for heat radiation
    20, 20a, 20b, 20c, 20d: chip
    22, 22a, 22b, 22c, 22d: collector electrode
    24, 24a, 24b, 24c, 24d: emitter electrode (main electrode)
    26: gate electrode (control electrode)
    30, 30a, 30b, 30c, 30d, 62, 64, 66: lead
    32, 32a, 32b, 32c, 32d: electrode connecting member
    34, 34c: external connecting terminal
    36: joining surface (with solder)
    37: edge portion of joining surface on gate electrode side
    38, 38a, 38b, 38c: projecting portion
    40, 40c, 40d, 46, 46c, 46d: solder
    41, 45: solder material
    50: assembled body
    70: wire
    80: resin
    权利要求:
    Claims (8)
    [1]
    Conclusions
    A semiconductor device comprising:
    a substrate with a semiconductor chip array surface;
    a semiconductor chip disposed on the semiconductor chip array surface and comprising a main electrode and a control electrode formed on a surface of the semiconductor chip on a side opposite a surface of the semiconductor chip surface opposite the semiconductor chip array surface, the control electrode formed on a remote position of the main electrode; and a wiring (English: "lead") with an electrode connection member (English: "electrode connecting member") of which at least a part is connected to the main electrode via a soldering, wherein viewed from a top view, the electrode connection member is a protruding part (English "Projecting portion") projecting toward a semiconductor chip side between an edge portion of a connection surface of the electrode connection member with the soldering on a control electrode side and the control electrode or at a position where the protruding part is in contact with the edge part of the connection surface of the electrode connection member with the soldering on the control electrode side.
    [2]
    The semiconductor device according to claim 1, wherein the projection, as viewed from a top view, is placed within an area where the semiconductor chip is placed.
    [3]
    3. A semiconductor device as claimed in Claim 1 or 2, wherein the protruding part is not in contact with the semiconductor chip.
    [4]
    The semiconductor device according to any of claims 1 to 3, wherein the protruding part is formed on the electrode connection part with an arrangement configuration capable of blocking the reach of a solder ball scattered from a side surface of the soldering to the control electrode at a connecting step of connecting the main electrode and the electrode connection member together by soldering.
    [5]
    5. A semiconductor device as claimed in any one of claims 1-4, wherein, as seen from a cross-section, the wiring is bent towards a semiconductor chip side at a part of the projecting part.
    [6]
    The semiconductor device according to any of claims 1 to 5, wherein, viewed from a surface of the electrode connection member on a side opposite to the surface of the electrode connection member facing the semiconductor chip arrangement surface, a recessed portion corresponding to the protruding portion is formed on the electrode connection part.
    [7]
    The semiconductor device according to any of claims 1-6, wherein, viewed from a top view, the electrode connection member is positioned so that the entire soldering is covered.
    [8]
    A method for manufacturing a semiconductor device for manufacturing the semiconductor device according to any of claims 1 to 7, the method for manufacturing a semiconductor device comprising:
    a semiconductor chip array step for arranging a semiconductor chip on a semiconductor chip array surface of a substrate having the semiconductor chip array surface such that a main electrode and a control electrode formed at a distance from the main electrode are positioned on a surface of the semiconductor chip on a side opposite a surface of the semiconductor chip that faces opposite to the semiconductor chip array surface;
    an assembled body-forming step (assembled body forming step) for forming an assembled body by arranging a wiring with an electrode connection member forming a protruding part on one surface thereof in an excellent manner in a state the main electrode and the electrode connection member being opposed to each other with a soldering material sandwiched therebetween, in a state where, as seen from a plan view, the protruding part is positioned between an edge portion of a connection surface of the electrode connection member with the soldering material on a control electrode side and the control electrode or at a position where the protruding portion is in contact with the edge portion of the connecting surface of the electrode connection member with the soldering material on the control electrode side, and in a state where the protruding portion protrudes toward a semiconductor chip. jde; and a connecting step for connecting the main electrode and the electrode connecting member together via a soldering by solidifying the solder material after melting the solder material.
    1/7
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